1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and particularly to a semiconductor memory which carries out reading and writing operations in order in one operating cycle. The present invention has particular applicability to dynamic random access memory device.
2. Description of the Background Art
FIG. 5 is a block diagram showing one example of a generally known conventional dynamic random memory (hereinafter, it is called as a DRAM). Referring to FIG. 5, this DRAM includes a memory array 58 provided with memory cells for storing data signals, an address buffer 54 which receives address signals from the outside, a row decoder 55 and a column decoder 56 both of which decode address signals, and a sense amplifier 63 which is connected to the memory array 58 to amplify and read out signals stored in memory cells. An input buffer 59 for inputting data signals and an output buffer 60 for outputting signals are connected via I/O lines 68 and an I/O gate 57 to the memory array 58.
A clock generator 51 is connected so as to receive a row address strobe signal RAS, a column address strobe signal CAS, an output enable signal OE, and a write enable signal WE all of which are provided from the outside and generates waveform-shaped signals of these signals and various clock signals. An I/O controller 65a is connected so as to receive signals which have been output by the clock generator 51 and controls a data input buffer 59 and a data output buffer 60.
FIG. 6A is a circuit diagram showing peripheral circuits of the memory array 58 of the DRAM shown in FIG. 5. FIG. 6B is a timing chart for explaining the operation of FIG. 5. These are shown, for example, in pp 252 to pp 253 of the digest of technical papers of the International Solid State Circuit Conference (ISSCC85) held in 1985.
Referring to FIG. 6A, a memory cell MC is connected between a bit line BLj and a word line WL1. The memory cell MC includes a capacitor Cs for storing data signals and a NMOS transistor Qs for switching. The sense amplifier 63 includes a CMOS flip-flop connected between the bit lines BLj and BLj. The CMOS flip-flop is connected via a PMOS transistor Q11 and a NMOS transistor Q12 to a power source Vcc and a ground Vss. The transistors Q11 and Q12 are connected in such a manner that gates thereof receive trigger signals So and So, respectively.
A bit line pre-charge voltage (Hereinafter, it is called as V.sub.BL) generating circuit is connected via an equalizing circuit 61 to the pair of bit lines BLj and BLj. An I/O gate 57 composed of NMOS transistors Q8 and Q9 are connected between the pair of bit lines BLj and BLj and a pair of I/O lines 63. The transistors Q8 and Q9 are connected in such a manner that gates thereof receive a signal Yj from a column decoder. A signal generating circuit 64 is provided in order to generate control signals PR, EQ, So and So for controlling these circuits.
Next, referring to FIG. 6A and FIG. 6B, the reading operation and writing operation of the DRAM will be described.
At first, the equalizing signal EQ and the precharge signal PR are generated from the signal generating circuit 64. In response to these signals, transistors Q10, Q5, Q6 and Q7 are turned on, and the pair of bit lines BLj and BLj are equalized and brought into the voltage of V.sub.BL (In this example, it is a voltage Vcc/2). After the signal RAS falls, the signals EQ and PR fall to a low level. Subsequently, a word line signal WLi rises up to a high level, and a switching transistor Qs of the memory cell MC is turned on. The voltage of the bit line BLj varies slightly by receiving a signal from the memory cell MC. By this, a very small voltage difference is produced between the bit line BLj and the bit line BLj having the voltage V.sub.BL.
On the other hand, at this time, the signals So and So vary, and the sense amplifier 63 is activated. As a result, the very small voltage difference generated between the bit lines is amplified by the sense amplifier 63. After this, the amplified data signal is provided via the transistors Q8 and Q9 to the pair of I/O lines 68 from the outside. In the case where this data signal is written into memory cell MC shown in FIG. 6A, the high level signals Yj and WLi are provided. As a result, the data signal to be written is stored via the transistor Q8, the bit line BLj, and the switching transistor Qs in a capacitor Cs.
FIG. 7 is a block diagram showing the circuit connections of the data input buffer 59, the data output buffer 60, and the I/O controller 65a to their peripheral circuits shown in FIG. 5. Referring to FIG. 7, the data output buffer 60 includes a preamplifier 601 connected thereto so as to receive a signal from the pair of I/O lines 68 and a main amplifier 602 connected to the output of the preamplifier 601. The preamplifier 601 is connected so as to receive a signal PE for activating thereof from the I/O controller 65a. The main amplifier 602 is also connected so as to receive a signal ME for activating thereof. The output of the main amplifier 602 is connected to an input/output terminal. On the other hand, the data input buffer 59 is connected via the data input/output terminal so as to receive the data signal to be written from the outside. The output of the data input buffer 59 is connected to the pair of I/O lines 68. The data input buffer 59 is connected so as to receive a switching control signal DBE from the I/O controller 65a.
The I/O controller 65a is connected to the clock generator 51 so as to receive the signals RAS; CAS, WE. and OE all of which are waveform-shaped by the clock generator 51. The I/O controller 65a includes an output control circuit 1 for controlling the data output buffer 60 and a writing control circuit 2 for controlling the data input buffer 59. The output control circuit 1 supplies the signal PE to the preamplifier 601 and the signal ME to the main amplifier 602. The writing control circuit 2 supplies the signal DBE to the data input buffer 59.
Now, the signals RAS and CAS provided from the outside can be understood as those which control a state of a DRAM. One operation cycle of the DRAM is provided by one cycle of a state control signal. For example, a period till the signal RAS falls again after it has fallen and risen up is called as one cycle.
The DRAM has an ordinary reading cycle (or reading mode) during which a reading operation is carried out one time and its ordinary writing cycle (or writing mode) during which its writing operation is done one time in its one cycle. In addition to this, the DRAM has a mode in which its reading and writing operations are carried out in order. In other words, the DRAM can carry out operations in a read-write cycle (mode) and a read modify write cycle (mode).
FIG. 8A is a timing chart for explaining the operation in an ordinary reading cycle of the DRAM shown in FIG. 7. Referring to FIG. 7 and FIG. 8A, in an ordinary reading operation, the signals RAS and CAS fall in order. An address signal AD is input in response to these signals, and a row address signal RA and a column address signal CA are held in the DRAM. The memory cell MC is specified by decoding the held signals RA and CA. The sense amplifier 63 amplifies and reads out a data signal stored in the memory cell MC. The I/O gate 57 is turned on in response to a signal Y obtained by decoding the signal CA, and the data signal from the memory cell MC is provided to the pair of I/O lines 68.
Next, the output enable signal OE falls. The output control circuit 1 in the I/O controller 65a outputs the activating signals PE and ME in order in response to the signal OE. The preamplifier 601 and the main amplifier 602 are activated respectively in response to the signals PE and ME to amplify the data signal on the pair of I/O lines 68. The amplified data signal Dout is output via the data input/output terminal to the outside. The time Tr required for these operations, that is, the ordinary reading cycle from the time till the signal RAS begins to fall until it has risen and begins to fall again, is for example about 190 ns.
FIG. 8B is a timing chart for explaining the operation in an ordinary writing cycle of the DRAM shown in FIG. 7. Referring to FIG. 7 and FIG. 8B, the row address signal RA and the column address signal CA are held in response to falling of the signals RAS and CAS. A data signal to be written Din is provided via the data input/output terminal. The data input buffer 59 receives the data signal Din to provide it to the pair of I/O lines 68 in response to the signal DBE from the writing control circuit 2. When the data signal Din is written in the memory MC shown in FIG. 7, the I/O gate 57 is turned on in response to the signal Y obtained by decoding the signal CA. Since the switching transistor Qs in the memory cell MC is turned on in response to the signal obtained by decoding the row address signal RA, the data signal Din is stored in the capacitor Cs. The time Tw required for the operation, that is, the ordinary writing cycle is, for example, about 190 ns.
FIG. 8C is a timing chart for explaining the operation in an ordinary read-write cycle of the DRAM shown in FIG. 7. Referring to FIG. 7 and FIG. 8C, in the first half of the read-write operation cycle, at first, the signals RAS and CAS fall in order. The row address signal and the column address signal CA are held in response to these signals. In the same way as an ordinary reading operation, the data signal stored in the memory cell MC specified by the address signals RA and CA is read out to the pair of I/O lines 68. The preamplifier 601 and the main amplifier 602 are activated in response to the signals PE and ME from the output control circuit 1 in order. As a result, the read out data signal Dout is output via the data input/output terminal.
In the second half of the operation cycle, the activation of the main amplifier 602 is completed in response to the rise of the signal OE. Next, the data signal Din to be written is provided via the data input/output terminal. The data input buffer 59 receives this data signal Din and provides it to the pair o I/O lines 68 in response to the signal DBE from the writing control circuit 2. The data signal Din provided to the pair of I/O lines 68 is written into the memory cell MC specified by the address signals RA and CA in the same way as an ordinary writing operation. The time Trw required for these operations, that is, for those in the read-write cycle becomes, for example, about 245 ns.
In a conventional DRAM, the time (for example, about 245 ns) required for the operations in the above mentioned read-write cycle and read-modify-write cycle is longer than the time (for example, 190 ns) required for an ordinary reading operation or writing operation. The reason is that in the one operation cycle, the writing operation is started after having completed the reading operation.